The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a recess gate.
As semiconductor devices become highly integrated, a channel length of a memory cell transistor decreases. Furthermore, as an ion implantation doping concentration to a substrate increases, junction leakage also increases due to an increasing electric field. Thus, it may be difficult to secure refresh characteristics of a semiconductor device with a typical planar type transistor structure.
Thus, a three-dimensional (3D) recess gate process has been introduced to overcome the above limitations. According to the process, a portion of an active region in a substrate is etched to form a recess increasing the channel length and a gate electrode is formed over the recess.
FIGS. 1A and 1B illustrate micrographic views of a transistor including a typical recess gate. FIG. 1A illustrates a cross-sectional view in a longitudinal direction of an active region and FIG. 1B illustrates a cross-sectional view in a lateral direction of the active region.
Referring to FIG. 1A, an isolation layer 12 is formed in the substrate 11 to define an active region and a recess 13 is formed by selectively etching a portion of the substrate 11 in the active region. The refresh characteristics of a semiconductor device may be secured as the channel length is increased by the recess 13. However, as a design rule of the semiconductor device becomes smaller, a critical dimension (CD) of the recess 13 is getting smaller. Thus, the profile of the recess 13 may be deteriorated as the profile of the bottom of the recess 13 becomes sharp due to decrease of its radius of curvature.
Referring to FIG. 1B, as the profile of the bottom of the recess 13 becomes sharp, a horn 100 is formed on an interface between the isolation layer 12 and the recess 13. Since the horn 100 may become a source of leakage current, the refresh characteristics of the semiconductor device may be deteriorated. Thus, a bulb-type recess gate process has been introduced to overcome the above limitations. According to the process, the bottom of the recess 13 is shaped roundly to increase the radius of curvature.
FIGS. 2A and 2B illustrate a micrographic view of profiles of a typical bulb-type recess gate. FIG. 2A illustrates a cross-sectional view in a longitudinal direction of an active region and FIG. 2B illustrates a cross-sectional view in a lateral direction of the active region.
Referring to FIG. 2A, an isolation layer 22 is formed in a substrate 21 to define an active region and a portion of the active region is selectively etched to form a bulb-type recess region 23. The bulb-type recess region 23 is formed to have a lower portion whose profile is round and wider in longitudinal direction than that of an upper portion of the bulb-type recess region 23.
As shown in FIG. 2B, a horn is not formed on an interface between the isolation layer 22 and the bulb-type recess region 23 due to forming the bulb-type recess region 23.
Meanwhile, forming the bulb-type recess region 23 should be performed as follows. After a first recess (not shown) having a vertical profile is formed by selectively etching the substrate 21, a passivation layer (not shown) is formed over sidewalls of the first recess to protect the sidewalls of the first recess during a subsequent etching process to form a second recess (not shown). The second recess is formed by isotropically etching a bottom of the first recess.
Typically, the passivation layer has been a thermal oxide layer such as a high temperature oxide (HTO) layer or a low pressure tetraethyloxysilane (LPTEOS) layer. When the thermal oxide layer is formed as the passivation layer, it requires a process time more than 5 hours and it is difficult to control a thickness of the thermal oxide layer. Furthermore, when the passivation layer is formed by using the thermal oxide layer, a thickness of the passivation layer on the bottom portion of the first recess may be greater than that on the sidewalls of the first recess, in which case the second recess may not be formed if an etching target thickness of the subsequent etching process is not sufficient to break through the thick oxide layer on the bottom of the first recess.
FIG. 3 illustrates a micrographic view of above problem of typical process using the thermal oxide layer as the passivation layer.
FIGS. 4A and 4B illustrate micrographic views of typical bulb-type recess gates, showing another problem called as a seam (400A and 400B) formed during formation of a gate electrode by filling a polysilicon layer in the recess pattern. Since the second recess is formed by an isotropic etching, it is difficult to control a CD of the second recess. And in case that a thermal oxide layer is used as the passivation layer, it becomes more difficult to control the CD of the second recess due to non-uniform thickness of the thermal oxide layer, which may cause unwanted increase in the CD of the second recess. On one hand, during a subsequent process to form a polysilicon gate electrode, a polysilicon layer having good step coverage is formed along the surface profile of the recess pattern. Therefore, in case that the CD of the second recess is excessively greater than that of the first recess, a space 400A is formed in the second recess, which is called as a seam. As illustrated with a reference numeral 400B in FIG. 4B, the seam 400A moves to an interface between a gate oxide layer and the polysilicon gate electrode during subsequent thermal processes, which deteriorates the refresh characteristics of a semiconductor device.